Even though integrated circuits are commonly thought of a being "small" in the ordinary sense of the term, there is another sense in which the distance from one side to another of a chip can be thought of as being a long distance indeed. Some of the driving forces behind today's modern complicated LSI IC's are that device geometry has gotten small while process yield has gone up, allowing an increase in die size. These trends combine to allow the production of very complicated mechanisms on a single die. The shrinking of device geometries has been accompanied by an increase in operating speed, even though power levels have also decreased. As a consequence, today's IC designers must cope with circumstances where they are forced to choose among trade-offs that relate power dissipation, speed and distance. That is, to get a set of high speed signals from one side of the chip to the other may require either greater amounts of silicon real estate for high power drivers or a reduction in operating speed.
In some cases the nature of the function the IC is to perform lends itself to another solution. Let's say that the IC is to operate upon a set of data, and that the data needs to be at more than one place on the chip. Often, the data can be serialized and sent across the chip to a shift register. Once in the shift register, the data may be shifted out as needed if continued serial use is desired, or it may be taken out "sideways" as parallel data. This mode of data transport has the advantage that only the clocking signal(s) and the serial data line need be routed across the distance to be covered.
Alas, genuine transmission lines (i.e., ones that sustain propagation of electromagnetic radiation without radiating it and with negligible dissipation) can be difficult to fabricate, and depending upon the IC process at hand, may not even be available. The result is that the pathways for clock signals and data from the source to the destination often look more like low pass filters than transmission lines. This slows up the edges of fast clock and data signals, and can require the lowering of data rates to ensure reliable operation. Thus, while the rest of the chip might operate at 50 or 100 MHz, the serial data path could be restricted to limping along at 10 or 20 MHz. It would be desirable if there were a way to cope with such lossy transmission lines and despite them, boost the data rates over such a serial path to a destination.